Conventional MOS FET devices are typically comprised of a gate electrode overlying a channel region and separated therefrom by a gate oxide. Conductive regions are formed in the substrate on either side of the gate electrode and the associated channel to form the source and drain regions. However, the major portion of the source and drain regions is utilized to provide a conductive path to the source and drain junctions. The dimensions of the source and drain regions are a function of the design layout and the photolithographic steps required to align the various contact masks, the alignment tolerances, etc.
Conventionally, an MOS transistor is fabricated by first forming the gate electrode and then the source and drain regions followed by depositing a layer of interlevel oxide over the substrate. Contact holes are then patterned by a separate mask and contact holes cut through the interlevel oxide to expose the underlying source and drain regions. This separate mask step requires an alignment step whereby the mask is aligned with the edge of the gate electrode which is also the edge of the channel region. There is, of course, a predefined alignment tolerance which determines how far from the edge of the gate electrode the ideal location of the contact. For example, if the alignment tolerance were 1 micron, this would mean that the contact wall would be disposed one micron from the edge of the gate electrode on one side and one micron from the edge of the nearest structure on the opposite side thereof. This therefore results in a source or drain region having a dimension of two microns plus the width of the contact. The overall width is therefore defined by alignment tolerances, the width of the conductive interconnection and the minimal separation from adjacent structures. This therefore results in a significant amount of surface area dedicated primarily to mask alignment.
When MOS devices are utilized in a complementary configuration such as CMOS devices, the additional space required to account for alignment tolerances becomes more of a problem. This is due to the fact that CMOS devices inherently require a greater amount of substrate and surface area than either functionally equivalent Nor P-channel FET devices. For example, the CMOS device density in an integrated circuit can be up to 40% less than the device density achieved by using conventional NMOS technology.
This size disadvantage is directly related to the amount of substrate surface area required for alignment and processing latitudes in the CMOS fabrication procedure to insure that the N- and P-channel transistors are suitably situated with respect to the P-well. Additionally, it is necessary to isolate the N- and P-channel transistors from each other with fixed oxide layers with an underlying channel stop region. As is well known, these channel stops are necessary to prevent the formation of parasitic channels between neighboring transistors. Typically, the channel stops are highly doped regions formed in the substrates surrounding each transistor and effectively block the formation of parasitic channels by substantially increasing the substrate surface inversion threshold voltage. Also, they are by necessity the opposite in conductivity type from the source and drain regions they are disposed adjacent to in order to prevent shorting. This, however, results in the formation of a highly doped, and therefore, low reverse breakdown voltage P-N junctions. Of course, by using conventional technology with the channel stops, there is a minimum distance by which adjacent transistors must be separated in order to prevent this parasitic channel from being formed and to provide adequate isolation.